1. Field of the Invention
This invention relates to the field of DC voltage generators and in particular to a DC voltage generator for generating low-standby current intermediate DC voltage levels for use in integrated circuits.
2. Background Art
Certain integrated circuit applications require low power operation. For example, CMOS-based (complementary metal oxide semiconductor) integrated circuits are typically low-power circuits. In addition, it is often desired to minimize power consumption such as in portable computers or battery-operated devices.
The operation of integrated circuits often requires that a signal be compared to a reference level such as a reference voltage. An on-chip DC voltage generator is often used to bias the capacitor plate of the DRAM memory array to ensure the optimum and reliable operation of memory cells. These reference voltages are typically generated by a DC voltage generator. An example of a DC voltage generator is illustrated in FIG. 1.
The prior art voltage generator of FIG. 1 consists of two complementary pairs of source coupled transistors. The first pair receives drain and gate current from a pair of biasing circuit to convert a supply voltage to some desired reference voltage. The second complementary pair of transistors are gate coupled to the drains of the first pair of transistors. This second pair of transistors functions as driver transistors and provide an output at their source coupled junction.
Referring to FIG. 1, the DC generator consists of a first complementary pair of transistors N1 and P1, a second pair complementary transistors N2 and P2 and bias circuits 11 and 15. VCC supply voltage 10 is provided to bias circuit 11. Bias circuit 11 provides an output at node 12 which is the drain of transistor N1. Node 12 is also coupled to the gate of transistor N1. The source of transistor N1 is coupled to the source of transistor P1 at node 13. Node 13 is also coupled to the body of transistor P1. The gate of transistor P1 is coupled to the drain of transistor P1 at node 14. Node 14 is coupled to bias circuit 15. Bias circuit 15 is also coupled to ground. Bias circuit 11 and bias circuit 15 can be any suitable bias circuit for providing a bias current at nodes 12 and 14 respectively. The voltage at node 13, V.sub.REF, is the desired reference voltage of the circuit.
VCC supply voltage 10 is also coupled to the drain of transistor N2. The gate of transistor N2 is coupled to node 12 and the source of transistor N2 is coupled to node 16. Node 16 is coupled to the source of transistor P2. The drain of transistor P2 is coupled to ground and the gate of transistor P2 is coupled to node 14. Transistors N2 and P2 are drive transistors and provide an output voltage V.sub.OUT at node 16. V.sub.OUT is approximately equal to V.sub.REF.
The voltage at node 12 is given by V.sub.REF +V.sub.TN1. The voltage at node 14 is given by V.sub.REF -.vertline.V.sub.TP1 .vertline. (the turn-on voltage of transistor P1). These voltages are provided to the gates of transistors N2 and P2 respectively. The gate source voltage of transistors N2 and P2 are given by the following: EQU V.sub.GS(N2) =(V.sub.REF +V.sub.TN1)-V.sub.OUT EQU V.sub.GS(P2) =(V.sub.REF -.vertline.V.sub.Tp1 .vertline.)-V.sub.OUT
Therefore, the output voltage V.sub.OUT at node 16 will be clamped in between V.sub.OUTN and V.sub.OUTP, which are given by the following: EQU V.sub.OUTN =V.sub.REF +V.sub.TN1 -V.sub.TN2 =V.sub.REF -(V.sub.TN2 -V.sub.TN1) EQU .sub.VOUTP =V.sub.REF -.vertline.V.sub.TP1 .vertline.+.vertline.V.sub.TP2 .vertline.=V.sub.REF +(.vertline.V.sub.TP2 .vertline.-.vertline.V.sub.TP1 .vertline.),
where V.sub.TN2 and V.sub.TP2 are the turn on voltages of transistors N2 and P2.
A disadvantage of prior art voltage generators is an inability to provide intermediate reference voltages that have stable low-standby current capability with wide process margins. This is due in part to the relationship between the transistors N1, N2, P1 and P2. The turn on voltage, VTN2, of transistor N2 is typically less than or equal to the turn on voltage VTN1 of transistor N1. The turn-on voltage, V.sub.TP2 of transistor P2 is typically less than or equal to the turn-on voltage V.sub.TP1 of transistor P1. Therefore, both driver transistors N2 and P2 could be on at the same time, as illustrated in FIG. 5, and draw hundreds on micro-amperes of current while operating in standby modes. Referring to FIG. 5, a plot of output voltage versus supply voltage is illustrated. In the operating range of the circuit, there is a region 50 in which both N2 and P2 are on, drawing current. This is not effective for low standby current operations.
The relationship of the turn on voltages of transistors N1 and N2 is affected by channel length and channel width. Transistor N1 has an associated width WN1 and channel length LN1. Transistor P1 has a width WP1 and a length LP1. Transistor N2 has a width WN2 and a length LN2, and transistor P2 has a width WP2 and a length LP2.
The channel length of transistors N1 and N2 are approximately equal. That is, LN1 is approximately equal to LN2. In addition, the channel length of transistors P1 and P2 are approximately equal so that LP1 is approximately equal to LP2.
For transistors with fixed transistor widths, the threshold voltages decrease with decreasing channel length. This is known as the "short channel effect" and is illustrated in FIG. 3. FIG. 3 is a plot of the absolute value of threshold voltage VT (in volts) versus transistor channel length (in microns). For a transistor having a transistor width of 6-10 microns and channel length of approximately 0.6 microns, the threshold voltage has a value of approximately 0.6 volts. Threshold voltage is approximately 0.7 volts for a transistor having a channel length of approximately 1 micron. The threshold voltage increases with channel length and levels off at approximately 3.0 microns. The level-off point in FIG. 3 is dependent on the process technology used.
Threshold voltage V.sub.T is also dependent on transistor width. For transistors with fixed channel lengths, the threshold voltages increase with decreasing transistor width. The effect of transistor width on threshold voltage is known as "narrow width effect" and is illustrated in FIG. 4. Threshold voltage is inversely proportional to transistor width at four low transistor widths. For example, the threshold voltage of a transistor having a channel length of 1.2 microns and a width of approximately 2 microns is approximately 1.3 volts. The threshold voltage of a transistor having the width of approximately 4 microns is approximately 0.95 volts. The threshold voltage decreases with increasing transistor width and levels off at greater transistor widths, on the order of 8-10 microns. The level-off point in FIG. 4 is dependent on the process technology used.